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TDA4VEN...Q1 数据表(PDF) 52 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 52 Page - Texas Instruments |
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52 / 236 page  Table 5-11. DDRSS0 Signal Descriptions (continued) SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] DDR0_DQS1 IO DDRSS Data Strobe H1 DDR0_DQS1_n IO DDRSS Complimentary Data Strobe J1 DDR0_DQS2 IO DDRSS Data Strobe T1 DDR0_DQS2_n IO DDRSS Complimentary Data Strobe U1 DDR0_DQS3 IO DDRSS Data Strobe W1 DDR0_DQS3_n IO DDRSS Complimentary Data Strobe Y1 DDR0_RESET0_n O DDRSS Reset U6 (1) DDRSS implements different signal functions on Column Address Strobe, Row Address Strobe, Chip Select 0, and Chip Select 1 when configured to operate with LPDDR4 memory devices. These signals function as Chip Select 1B, Chip Select 0B, Chip Select 0A, and Chip Select 1A respectively when DDRSS is configured to operate with LPDDR4 memory devices. For more information, refer to Section 8.2.1, DDR Board Design and Layout Guidelines. (2) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. 5.3.5 DSI 5.3.5.1 MAIN Domain Table 5-12. DSITX0 Signal Descriptions SIGNAL NAME [1] ((2)) PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] DSI0_TXCLKN IO DSI Differential Transmit Clock Ouput (negative) AE16 DSI0_TXCLKP IO DSI Differential Transmit Clock Ouput (positive) AE17 DSI0_TXRCALIB (1) A DSI pin connected to external resistor for on-chip resistor calibration AA16 DSI0_TXN0 IO DSI Differential Transmit Ouput (negative) AD17 DSI0_TXN1 IO DSI Differential Transmit Ouput (negative) AF15 DSI0_TXN2 IO DSI Differential Transmit Ouput (negative) AG14 DSI0_TXN3 IO DSI Differential Transmit Ouput (negative) AC18 DSI0_TXP0 IO DSI Differential Transmit Ouput (positive) AD18 DSI0_TXP1 IO DSI Differential Transmit Ouput (positive) AF16 DSI0_TXP2 IO DSI Differential Transmit Ouput (positive) AG15 DSI0_TXP3 IO DSI Differential Transmit Ouput (positive) AC19 (1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is 7.2mW. No external voltage should be applied to this pin. (2) The functionality of these pins is controlled by DPHY_TX0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = DSI PPI, 0x1 = CSI0 TX. 5.3.6 DSS 5.3.6.1 MAIN Domain Table 5-13. DSS0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] AMW PIN [4] VOUT0_DE O Video Output Data Enable AC27 VOUT0_EXTPCLKIN I Video Output External Pixel Clock Input W26 VOUT0_HSYNC O Video Output Horizontal Sync AB24 VOUT0_PCLK O Video Output Pixel Clock Output AC26 VOUT0_VSYNC O Video Output Vertical Sync AB23 VOUT0_DATA0 O Video Output Data 0 W27 VOUT0_DATA1 O Video Output Data 1 W25 VOUT0_DATA2 O Video Output Data 2 W24 VOUT0_DATA3 O Video Output Data 3 W23 TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 52 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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