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TDA4VEN...Q1 数据表(PDF) 20 Page - Texas Instruments

部件名 TDA4VEN...Q1
功能描述  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VEN...Q1 数据表(HTML) 20 Page - Texas Instruments

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Table 5-1. Pin Attributes (AMW Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL STATE
DURING
RESET
(RX/TX/PULL) [7]
BALL STATE
AFTER
RESET
(RX/TX/PULL) [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
V24
GPMC0_AD13
PADCONFIG
PADCONFIG28
0x000F4070
GPMC0_AD13
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA21
1
O
UART4_TXD
2
O
MCASP2_ACLKX
3
IO
0
TRC_DATA21
6
O
GPIO0_28
7
IO
pad
BOOTMODE13
Bootstrap
I
V22
GPMC0_AD14
PADCONFIG
PADCONFIG29
0x000F4074
GPMC0_AD14
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA22
1
O
UART5_RXD
2
I
1
MCASP2_AFSR
3
IO
0
MCASP2_AXR4
4
IO
0
TRC_DATA20
6
O
GPIO0_29
7
IO
pad
UART2_CTSn
8
I
1
BOOTMODE14
Bootstrap
I
V23
GPMC0_AD15
PADCONFIG
PADCONFIG30
0x000F4078
GPMC0_AD15
0
IO
0
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
VOUT0_DATA23
1
O
UART5_TXD
2
O
MCASP2_ACLKR
3
IO
0
MCASP2_AXR5
4
IO
0
TRC_DATA19
6
O
GPIO0_30
7
IO
pad
UART2_RTSn
8
O
BOOTMODE15
Bootstrap
I
P27
GPMC0_BE0n_CLE
PADCONFIG
PADCONFIG36
0x000F4090
GPMC0_BE0n_CLE
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
MCASP1_ACLKX
2
IO
0
TRC_DATA10
6
O
GPIO0_35
7
IO
pad
P26
GPMC0_BE1n
PADCONFIG
PADCONFIG37
0x000F4094
GPMC0_BE1n
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
MCASP2_AXR12
3
IO
0
TRC_DATA11
6
O
GPIO0_36
7
IO
pad
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
www.ti.com
20
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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