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TDA4VEN...Q1 数据表(PDF) 21 Page - Texas Instruments

部件名 TDA4VEN...Q1
功能描述  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VEN...Q1 数据表(HTML) 21 Page - Texas Instruments

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Table 5-1. Pin Attributes (AMW Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL STATE
DURING
RESET
(RX/TX/PULL) [7]
BALL STATE
AFTER
RESET
(RX/TX/PULL) [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
R27
GPMC0_CSn0
PADCONFIG
PADCONFIG42
0x000F40A8
GPMC0_CSn0
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
I2C4_SCL
1
IOD
1
MCASP2_AXR14
3
IO
0
TRC_DATA15
6
O
GPIO0_41
7
IO
pad
P21
GPMC0_CSn1
PADCONFIG
PADCONFIG43
0x000F40AC
GPMC0_CSn1
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
I2C4_SDA
1
IOD
1
MCASP2_AXR15
3
IO
0
TRC_DATA16
6
O
GPIO0_42
7
IO
pad
P22
GPMC0_CSn2
PADCONFIG
PADCONFIG44
0x000F40B0
GPMC0_CSn2
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
I2C2_SCL
1
IOD
1
MCASP1_AXR4
2
IO
0
UART4_RXD
3
I
1
MCAN1_TX
5
O
TRC_DATA17
6
O
GPIO0_43
7
IO
pad
MCASP1_AFSR
8
IO
0
P23
GPMC0_CSn3
PADCONFIG
PADCONFIG45
0x000F40B4
GPMC0_CSn3
0
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
I2C2_SDA
1
IOD
1
GPMC0_A20
2
OZ
UART4_TXD
3
O
MCASP1_AXR5
4
IO
0
MCAN1_RX
5
I
1
TRC_DATA18
6
O
GPIO0_44
7
IO
pad
MCASP1_ACLKR
8
IO
0
V21
GPMC0_WAIT0
PADCONFIG
PADCONFIG38
0x000F4098
GPMC0_WAIT0
0
I
1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
MCASP1_AFSX
2
IO
0
TRC_DATA12
6
O
GPIO0_37
7
IO
pad
www.ti.com
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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