TDA4VEN...Q1 datasheet(2/236 Pages) TI

2 / 236 page

– 512KB of On-chip RAM with SECDED ECC in

Cortex-R5F MCU Subsystem

– 64KB of On-chip RAM with SECDED ECC in

R5F Device Manager Subsystem

– 64KB of On-chip RAM with SECDED ECC in

R5F Run-time Manager Subsystem

– 2.25MB of L2 SRAM with SECDED ECC in

each C7x Deep Learning Accelerator (up to

4.5MB total)

• DDR Subsystem (DDRSS)

– Supports LPDDR4 memory types

– 32-bit data bus with inline ECC

– Supports speeds up to 4000 MT/s

– Max LPDDR4 size of 8GB

Functional Safety:

• Functional Safety-Compliant targeted for

Automotive (on select part numbers)

– Developed for functional safety applications

– Documentation will be available to aid ISO

26262 functional safety system design

– Systematic capability up to ASIL D targeted

– Hardware integrity up to ASIL B targeted

– Safety-related certification

• ISO 26262 planned

• AEC - Q100 qualified

Security:

• Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Trusted Execution Environment (TEE) supported

– Arm TrustZone® based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

– Secure storage support

– Replay Protected Memory Block (RPMB)

support

• Dedicated Security Controller with user

programmable HSM core and dedicated security

DMA & IPC subsystem for isolated processing

• Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

• Supports cryptographic cores

– AES – 128-/192-/256-Bit key sizes

– SHA2 – 224-/256-/384-/512-Bit key sizes

– DRBG with true random number generator

– PKA (Public Key Accelerator) to Assist in

RSA/ECC processing for secure boot

• Debugging security

– Secure software controlled debug access

– Security aware debugging

High-Speed Interfaces:

• PCI-Express® Gen3 single lane controller (PCIE)

– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3

(8.0GT/s) operation with auto-negotiation

• Integrated Ethernet switch supporting (total 2

external ports)

– RMII(10/100) or RGMII (10/100/1000) or SGMII

(1Gbps)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Time Sensitive Networking (TSN) support

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

• USB3.1-Gen1 Port

– One enhanced SuperSpeed Gen1 port

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device

– Integrated USB VBUS detection

• USB2.0 Port

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

• 9x Universal Asynchronous Receiver-Transmitters

(UART)

• 5x Serial Peripheral Interface (SPI) controllers

• 7x Inter-Integrated Circuit (I2C) ports

• 5x Multichannel Audio Serial Ports (McASP)

• General-Purpose I/O (GPIO), All LVCMOS I/O can

be configured as GPIO

• 4x Controller Area Network (CAN) modules with

CAN-FD support

Media and Data Storage:

• 3x Secure Digital® (SD®) (4b+4b+8b) interfaces

– 1x 8-bit eMMC interface up to HS400 speed

– 2x 4-bit SD/SDIO interfaces up to UHS-I

– Compliant with eMMC 5.1, SD 3.0, and SDIO

Version 3.0

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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