 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TDA4VEN...Q1 数据表(PDF) 8 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TDA4VEN...Q1 数据表(HTML) 8 Page - Texas Instruments |
|
|
8 / 236 page  5 Terminal Configuration and Functions 5.1 Pin Diagrams Note The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Figure 5-1 shows the ball locations for the 594-ball flip chip ball grid array (FCBGA) package to quickly locate signal names and ball grid numbering. This figure is used in conjuction with Section 5.2.1 through Section 5.4 (Pin Attributes table and all Signal Descriptions tables, including the Pin Connectivity Requirements table). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG Not to scale VSS WKUP _LFOSC0 _XO WKUP _LFOSC0 _XI VSS MCU_OSC0 _XI MCU_OSC0 _XO VSS PMIC_LPM _EN0 MCU_SPI0 _CLK MCU_SPI0 _CS1 TCK SERDES1 _TX0_N SERDES1 _TX0_P SERDES0 _REFCLK0P SERDES0 _REFCLK0N VSS SERDES0 _RX0_P SERDES0 _RX0_N VSS I2C1_SDA EXT _REFCLK1 MMC1_SDWP MCASP0 _AXR3 MCASP0 _AXR2 VSS MCU_MCAN1 _RX MCU_MCAN0 _TX WKUP _UART0 _RXD MCU_UART0 _TXD MCU_UART0 _CTSn RSVD16 MCU _ERRORn MCU_UART0 _RXD WKUP_I2C0 _SCL TRSTn MCU_SPI0 _D0 MCU_I2C0 _SCL SERDES1 _REFCLK0N SERDES1 _REFCLK0P SERDES0 _TX0_P SERDES0 _TX0_N SPI0_CS0 UART0 _RTSn I2C0_SDA EXTINTn MMC1_SDCD MCASP0 _AXR1 USB1 _DRVVBUS MCU_MCAN1 _TX VSS WKUP _UART0 _RTSn WKUP _UART0 _CTSn MCU_UART0 _RTSn RSVD14 WKUP _UART0 _TXD EMU0 MCU_SPI0 _D1 MCU_SPI0 _CS0 SERDES1 _RX0_N SERDES1 _RX0_P RSVD17 SPI0_CS1 MCAN0_RX VSS I2C1_SCL MCASP0 _AFSX MCASP0 _AFSR VDDS_DDR DDR0_DQ1 DDR0_DQ3 DDR0_DQ0 MCU_MCAN0 _RX MCU _RESETz WKUP_I2C0 _SDA RSVD20 RSVD19 RSVD18 USB1_DP SPI0_CLK MCAN0_TX I2C0_SCL MCASP0 _ACLKX VSS PORz_OUT DDR0_DQS0 DDR0_DQ5 VSS MCU_PORz RSVD0 MCU_I2C0 _SDA TDI MCU_RESETS TATz SERDES0 _REXT USB1_DM USB1 _RCALIB SPI0_D0 SPI0_D1 UART0 _CTSn USB0 _DRVVBUS RESET _REQz RESETSTA Tz DDR0_DQS0 _n VSS DDR0_DQ7 DDR0_DQ2 RSVD15 EMU1 TDO TMS WKUP _CLKOUT0 SERDES1 _REXT VSS VSS VSS USB1_VBUS UART0_RXD UART0_TXD VSS MCASP0 _AXR0 MCASP0 _ACLKR PCIE0 _CLKREQn MMC2_SDCD MMC2_CMD VSS DDR0_DM0 VSS DDR0_DQ4 VSS DDR0_DQ6 VMON_ER _VSYS VSS VPP VSS VDDA_MCU VSS VDDA_1P8 _SERDES VSS VDDA_3P3 _USB1 VSS VSS VDDSHV0 CAP_VDDS5 VSS MMC2_DAT0 MMC2_DAT1 DDR0_DQS1 DDR0_DQ9 DDR0_DQ15 VSS DDR0_DQ8 DDR0_DM1 VSS CAP_VDDS _CANUART VDDSHV _CANUART VDDSHV _MCU VDDA_MCU VDDA_0P85 _SERDES VDDA_0P85 _SERDES VSS VDDA_CORE _USB1 VDDA_1P8 _USB1 CAP_VDDS0 VDDSHV0 VDDSHV5 MMC1_DAT1 MMC2_SDWP MMC1_CMD MMC1_DAT0 MMC1_CLK MMC1_DAT3 MMC2_CLK MMC2_DAT2 DDR0_DQS1 _n DDR0_DQ14 VSS DDR0_DQ13 VSS DDR0_DQ12 VMON_1P8 _SOC VDD _CANUART VSS CAP_VDDS _MCU VDD_CORE VSS VDDA_0P85 _SERDES_C VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS CAP_VDDS6 VDDSHV6 OSPI0 _CSn3 MMC1_DAT2 VSS MMC2_DAT3 VSS DDR0_DQ10 VMON_3P3 _SOC VDDS_OSC0 VDD_CORE VDDA_PLL1 VDD_CORE VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDDSHV1 OSPI0 _CSn2 OSPI0 _CSn1 OSPI0 _CSn0 OSPI0_D0 DDR0_DQ11 DDR0_A5 DDR0_A3 DDR0_A0 RSVD10 DDR0_A1 VDDS_DDR VDDS_DDR VDDA _TEMP2 VSS VSS VDD_CORE VSS VSS VDDA_PLL0 VSS VDD_CORE VSS CAP_VDDS1 VDDSHV1 OSPI0_D4 OSPI0_DQS OSPI0 _LBCLKO OSPI0_CLK OSPI0_D3 OSPI0_D2 OSPI0_D1 VSS RSVD21 DDR0_RAS _n DDR0_CAS _n DDR0_A2 RSVD11 VSS VSS VDD_CORE VDD_CORE VSS VDDA_PLL2 VDDR_CORE VSS VDD_CORE VSS VDD_CORE VSS VDDR_CORE VDDSHV3 OSPI0_D5 OSPI0_D7 DDR0_CK0 _n DDR0_A4 VDDS_DDR VDDS_DDR VSS VDD_CORE VDD_CORE VSS VDDR_CORE VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDR_CORE CAP_VDDS3 GPMC0 _ADVn_ALE GPMC0_OEn _REn GPMC0_WEn GPMC0_WPn GPMC0_DIR VSS OSPI0_D6 DDR0_CK0 DDR0_CKE0 DDR0_CS1 _n DDR0_CS0 _n VSS DDR0_CKE1 VSS VDDS_DDR _C VDDA_DDR _PLL0 VSS VDD_CORE VDD_CORE VSS VDD_CORE VSS VDDA_PLL5 VSS VDD_CORE VSS VDDSHV3 GPMC0 _CSn1 GPMC0 _CSn2 GPMC0 _CSn3 GPMC0 _BE1n GPMC0 _BE0n_CLE VSS DDR0_DQ17 DDR0_DQ20 VSS DDR0_DQ18 DDR0_CAL0 VSS VSS VDD_CORE VSS VDDA_PLL3 VDD_CORE VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VSS VDDSHV3 GPMC0_AD0 GPMC0_AD1 GPMC0_AD2 GPMC0 _CSn0 DDR0_DQS2 DDR0_DQ19 VDDS_DDR VDDS_DDR VDD_CORE VSS VDDA _TEMP1 VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDDSHV2 VDDSHV2 GPMC0_AD6 GPMC0_AD7 GPMC0_CLK GPMC0_AD5 GPMC0_AD4 VSS GPMC0_AD3 DDR0_DQS2 _n DDR0_DQ21 VSS DDR0_DM2 DDR0_DQ22 DDR0 _RESET0_n VSS VDD_CORE VSS VDDR_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDR_CORE VSS VSS CAP_VDDS2 GPMC0_AD9 GPMC0_AD8 VSS DDR0_DQ23 DDR0_DQ16 VSS DDR0_DQ26 DDR0_DQ28 VSS VDD_CORE VSS VDDR_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDR_CORE VDDA_PLL4 VDD_CORE VSS GPMC0 _WAIT0 GPMC0 _AD14 GPMC0 _AD15 GPMC0 _AD13 GPMC0 _AD11 GPMC0 _AD12 GPMC0 _AD10 DDR0_DQS3 DDR0_DQ27 DDR0_DQ29 DDR0_DQ25 VSS USB0_VBUS VSS VDDA_0P85 _DLL_MMC0 VDD_MMC0 VDDA_CORE _USB0 VSS VDDA_1P8 _CSI_DSI VSS VDDA_CORE _CSI_DSI VDDA_1P8 _CSI_DSI VSS VDDA_1P8 _OLDI0 VDD_CORE VSS VOUT0 _DATA5 VOUT0 _DATA4 VOUT0 _DATA3 VOUT0 _DATA2 VOUT0 _DATA1 GPMC0 _WAIT1 VOUT0 _DATA0 DDR0_DQS3 _n DDR0_DQ24 VSS VSS VDDS_MMC0 VSS VDDA_3P3 _USB0 VDDA_1P8 _USB0 VDDA_1P8 _CSI_DSI VSS VDDA_CORE _CSI_DSI VDDA_CORE _CSI_DSI _CLK VDDA _TEMP0 VSS VDDA_1P8 _OLDI0 VDD_CORE VDD_CORE VOUT0 _DATA6 VOUT0 _DATA7 VSS DDR0_DM3 DDR0_DQ30 VSS DDR0_DQ31 USB0_DP USB0 _RCALIB CSI1 _RXRCALIB RSVD5 RSVD9 RSVD8 DSI0 _TXRCALIB VSS RSVD1 OLDI0_A7P VSS VOUT0 _DATA13 VOUT0 _DATA12 VOUT0 _DATA8 VOUT0 _DATA10 VSS VOUT0 _DATA9 VDDS_DDR MMC0_DAT7 MMC0_DAT5 MMC0_DAT2 USB0_DM RSVD2 CSI0 _RXRCALIB RSVD4 RSVD6 RSVD7 CSI2 _RXRCALIB CSI3 _RXRCALIB RSVD12 RSVD13 OLDI0_A7N OLDI0_A2N OLDI0_A2P VOUT0 _VSYNC VOUT0 _HSYNC VOUT0 _DATA11 VOUT0 _DATA14 VOUT0 _DATA15 MMC0 _CALPAD MMC0_DAT3 MMC0_DAT4 RSVD3 CSI0 _RXCLKP CSI0 _RXCLKN CSI1_RXP3 CSI1_RXN3 CSI2_RXP3 CSI2_RXN3 CSI3_RXN3 CSI3_RXP3 DSI0_TXN3 DSI0_TXP3 OLDI0_A4P MDIO0_MDC RGMII1 _RD0 VOUT0 _PCLK VOUT0_DE MMC0_DS MMC0_DAT1 MMC0_DAT0 CSI0_RXP0 CSI0_RXN0 CSI1_RXP2 CSI1_RXN2 CSI2_RXN2 CSI2_RXP2 CSI3_RXP2 CSI3_RXN2 DSI0_TXN0 DSI0_TXP0 OLDI0 _CLK1N OLDI0_A4N RGMII1_RX _CTL MDIO0 _MDIO VSS RGMII1 _RD1 MMC0_CLK MMC0_CMD CSI0_RXP1 CSI0_RXN1 CSI1_RXP1 CSI1_RXN1 CSI2_RXN1 CSI2_RXP1 CSI3_RXP1 CSI3_RXN1 DSI0 _TXCLKN DSI0 _TXCLKP OLDI0 _CLK1P OLDI0 _CLK0P RGMII1 _TD1 RGMII1 _RD2 RGMII1 _RD3 RGMII1 _RXC MMC0_DAT6 CSI0_RXP2 CSI0_RXN2 CSI1_RXP0 CSI1_RXN0 CSI2_RXN0 CSI2_RXP0 CSI3_RXP0 CSI3_RXN0 DSI0_TXN1 DSI0_TXP1 OLDI0_A5P OLDI0_A5N OLDI0 _CLK0N OLDI0_A0N RGMII1 _TD3 RGMII1_TX _CTL RGMII1 _TD0 VSS CSI0_RXP3 CSI0_RXN3 CSI1 _RXCLKP CSI1 _RXCLKN CSI2 _RXCLKN CSI2 _RXCLKP CSI3 _RXCLKP CSI3 _RXCLKN DSI0_TXN2 DSI0_TXP2 OLDI0_A6N OLDI0_A6P OLDI0_A3N OLDI0_A3P OLDI0_A1N OLDI0_A1P OLDI0_A0P RGMII1 _TD2 RGMII1 _TXC VSS Figure 5-1. AMW FCBGA-N594 Pin Diagram (Top View) TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
