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TDA4VEN...Q1 数据表(PDF) 1 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 1 Page - Texas Instruments |
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1 / 236 page  TDA4VEN, TDA4AEN Jacinto™ Processors 1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Arm® Cortex®-R5F at up to 800MHz, integrated as part of MCU Channel with FFI – 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories – 512KB SRAM with SECDED ECC • Single-core Arm® Cortex®-R5F at up to 800MHz, integrated to support Device Management – 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories • Single-core Arm® Cortex®-R5F at up to 800MHz, integrated to support Run-time Management – 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories • Two Deep Learning Accelerators (up to 4 TOPS total), each with: – C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz – Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz – 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection – 2.25MB of L2 SRAM with SECDED ECC • Depth and Motion Processing Accelerators (DMPAC) – Dense Optical Flow (DOF) Accelerator – Stereo Disparity Engine (SDE) Accelerator • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators: – 600 MP/s ISP – Support for 12-bit RGB-IR – Support for up to 16-bit input RAW format – Line support up to 4096 – Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL Multimedia: • Display subsystem – Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock) • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock) • MIPI® DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300- MHz Pixel Clock) • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock) – Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display. – Supports safety features such as freeze frame detection and data correctness check • 3D Graphics Processing Unit (TDA4VEN) – IMG BXS-4-64 with 256KB cache – Up to 50 GFLOPS – Single shader core – OpenGL ES3.2 and Vulkan 1.2 API support • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY – MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2 – CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane – CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI) • Video Encoder/Decoder – Support for HEVC (H.265) Main profiles at Level 5.1 High-tier – Support for H.264 BaseLine/Main/High Profiles at Level 5.2 – Support for up to 4K UHD resolution (3840 × 2160) • Up to 400MPixels/s operation • Motion JPEG encode at 416MPixels/s with resolutions up to 4K UHD (3840 × 2160) Memory Subsystem: • On-chip RAM dedicated to key processing cores – 256KB of On-Chip RAM (OCRAM) with SECDED ECC – 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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