TDA4VEN...Q1 datasheet(116/236 Pages) TI

116 / 236 page

Table 6-23. MCU_OSC0 LVCMOS Digital Clock Source Requirements

PARAMETER

MIN

TYP

MAX

UNIT

Fxtal

Frequency

MHz

Frequency Stability and Tolerance

Ethernet RGMII and RMII

not used

±100

ppm

Ethernet RGMII and RMII

using derived clock

±50

Duty Cycle

tR/F

Rise/Fall Time (10%-90% rise, 90%-10% fall)

4(1)

JPeriod(RMS)

Period Jitter, RMS (100k samples)

JPeriod(PK-PK) Period Jitter, Peak to Peak (100k samples)

300

JPhase(RMS)

Phase Jitter, RMS (BW 100Hz to 1MHz)

10(2)

(1)

Most LVCMOS oscillator datasheets define their maximum Output Rise/Fall times with a capacitive load much larger than the actual

load that will be applied by the combined PCB trace capacitance and MCU_OSC0_XI input capacitance. It should not be difficult to

find a LVCMOS oscillator that meets this requirement. However, the system designer must confirm the LVCMOS oscillator selected will

provide the appropriate rise/fall time to MCU_OSC0_XI input.

(2)

Most LVCMOS oscillator datasheets define their max RMS Phase Jitter using a larger bandwidth integration range than required by

this device. To get a more appropriate value, it may be necessary to contact the LVCMOS oscillator manufacture and ask them to

provide a maximum RMS Phase Jitter using the same bandwidth integration range that has been defined for this parameter.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

116

Submit Document Feedback

Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1

TDA4VEN...Q1 数据表(PDF) 116 Page - Texas Instruments

TDA4VEN...Q1 数据表(HTML) 116 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载