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TDA4VEN...Q1 数据表(PDF) 128 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 128 Page - Texas Instruments |
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128 / 236 page  Table 6-36. RGMII[x]_RXC Timing Requirements – RGMII Mode see Figure 6-31 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII1 tc(RXC) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(RXCH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(RXCL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns Table 6-37. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode see Figure 6-31 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII4 tsu(RD-RXC) Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(RX_CTL-RXC) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII5 th(RXC-RD) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(RXC-RX_CTL) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII[x] RD 3 _ [ :0] (B) RGMII[x] RX_CTL _ (B) RGMII[x] RXC _ (A) RGMII4 RXERR RXDV 2nd Half-byte 1st Half-byte RGMII2 RGMII3 RGMII1 RGMII5 A. RGMII[x]_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC. Figure 6-31. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII Mode TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 128 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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