TDA4VEN...Q1 datasheet(166/236 Pages) TI

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ASP8

ASP7

ASP4

ASP3

ASP2

ASP1

A0 A1

B0 B1

A30 A31

B30 B31 C0 C1 C2 C3

C31

MCASP[x]_AHCLKR/X (Falling Edge Priority)

MCASP[x]_AHCLKR/X (Rising Edge Polarity)

MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)

MCASP[x]_AXR[x] (Data In/Receive)

ASP6

ASP5

MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)

(A)

MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)

(B)

For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured

for falling edge (to shift data in).

For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured

for rising edge (to shift data in).

Figure 6-62. MCASP Timing Requirements

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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