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6.9.5.19.1 OSPI0 PHY Mode

6.9.5.19.1.1 OSPI0 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating

frequency. A data training method may be implemented to dynamically configure optimal read and write timing.

Implementing data training enables proper operation across temperature with a specific process, voltage, and

frequency operating condition, while achieving a higher operating frequency.

Data transmit and receive timing parameters are not defined for the data training use case since they are

dynamically adjusted based on the operating condition.

Table 6-113 defines DLL delays required for OSPI0 with Data Training. Table 6-114, Figure 6-95, Figure 6-96,

Table 6-115, Figure 6-97, and Figure 6-98 present timing requirements and switching characteristics for OSPI0

with Data Training.

Table 6-113. OSPI0 DLL Delay Mapping for PHY Data Training

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD

(1)

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

(2)

(1)

Transmit DLL delay value determined by training software

(2)

Receive DLL delay value determined by training software

Table 6-114. OSPI0 Timing Requirements – PHY Data Training

see Figure 6-95, and Figure 6-96

NO.

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

DDR with DQS

(1)

O16

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

DDR with DQS

(1)

O21

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

SDR with External Board Loopback

(1)

O22

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

SDR with External Board Loopback

(1)

tDVW

Data valid window (O15 + O16)

1.8V, DDR with DQS

1.6

3.3V, DDR with DQS

2.2

Data valid window (O21 + O22)

1.8V, SDR with External Board Loopback

2.3

3.3V, SDR with External Board Loopback

2.9

(1)

Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum

data valid window. The tDVW parameter defines the minimum data invalid window required. This parameter is provided in lieu of

minimum setup and minimum hold times, where it must be used to check compatibility with the data valid window provided by an

attached device.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

O16

O15

Figure 6-95. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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