TMP86FS49AIUG datasheet(154/296 Pages) TOSHIBA

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Page 138

11. 8-Bit TimerCounter (TC5, TC6)

11.1 Configuration

TMP86FS49AIUG

11.3.9.2 High-Frequency Warm-Up Counter Mode

(SLOW1

→ SLOW2 → NORMAL2 → NORMAL1)

In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta-

bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock.

When a match between the up-counter and the timer register (TTREG6, 5) value is detected after the timer

is started by setting TC6CR<TC6S> to 1, the counter is cleared by generating the INTTC6 interrupt

request. After stopping the timer in the INTTC6 interrupt service routine, clear SYSCR2<SYSCK> to 0 to

switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to

stop the low-frequency clock.

Table 11-9 Setting Time in High-Frequency Warm-Up Counter Mode

Minimum time (TTREG6, 5 = 0100H)

Maximum time (TTREG6, 5 = FF00H)

µs

4.08 ms

Example :After checking high-frequency clock oscillation stability with TC6 and 5, switching to the NORMAL1 mode

SET

(SYSCR2).7

: SYSCR2<XEN>

← 1

(TC5CR), 63H

: Sets TFF5=0, source clock fs, and 16-bit mode.

(TC6CR), 05H

: Sets TFF6=0, and warm-up counter mode.

(TTREG5), 0F800H

: Sets the warm-up time.

(The warm-up time depends on the oscillator characteristic.)

: IMF

← 0

SET

(EIRE). 2

: Enables the INTTC6.

: IMF

← 1

SET

(TC6CR).3

: Starts the TC6 and 5.

PINTTC6:

CLR

(TC6CR).3

: Stops the TC6 and 5.

CLR

(SYSCR2).5

: SYSCR2<SYSCK>

← 0

(Switches the system clock to the high-frequency clock.)

CLR

(SYSCR2).6

: SYSCR2<XTEN>

← 0

(Stops the low-frequency clock.)

RETI

VINTTC6:

PINTTC6

: INTTC6 vector table

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