TMP86FS49AIUG datasheet(182/296 Pages) TOSHIBA

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14. Synchronous Serial Interface (SIO1)

14.3 Function

TMP86FS49AIUG

(2)

During the transmit operation

When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0”.

In internal clock operation, in case a next transmit data is not written to SIO1TDB, the serial clock

stops to “H” level by an automatic-wait function when all of the bit set in the SIO1TDB has been

transmitted. Automatic-wait function is released by writing a transmit data to SIO1TDB. Then, trans-

mit operation is restarted after maximum 1-cycle of serial clock.

When the next data is written to the SIO1TDB before termination of previous 8-bit data with

SIO1SR<TXF> “1”, the next data is continuously transferred after transmission of previous data.

In external clock operation, after SIO1SR<TXF> is set to “1”, the transmit data must be written to

SIO1TDB before the shift operation of the next data begins.

If the transmit data is not written to SIO1TDB, transmit error occurs immediately after shift opera-

tion is started. Then, INTSIO1 interrupt request is generated after SIO1SR<TXERR> is set to “1”.

(3)

Stopping the transmit operation

There are two ways for stopping transmits operation.

• The way of clearing SIO1CR<SIOS>.

When SIO1CR<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the

data is finished. When transmit operation is finished, SIO1SR<SIOF> is cleared to “0” and

SO1 pin is kept in high level.

In external clock operation, SIO1CR<SIOS> must be cleared to “0” before SIO1SR<SEF> is

set to “1” by beginning next transfer.

• The way of setting SIO1CR<SIOINH>.

Transmit operation is stopped immediately after SIO1CR<SIOINH> is set to “1”. In this

case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and SIO1TDB register are ini-

tialized.

Figure 14-6 Example of Internal Clock and MSB Transmit Mode

A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1

C6 C5 C4 C3 C2 C1 C0

Automatic wait

Start shift

operation

Start shift

operation

Start shift

operation

Writing transmit

data B

Writing transmit

data A

Writing transmit

data C

Clearing SIOS

SIO1CR<SIOS>

SIO1SR<SIOF>

SIO1SR<SEF>

SCK1

pin output

SO1 pin

SIO1SR<TXF>

SIO1TDB

INTSIO1

interrupt

request

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