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TMP86FS49AIUG 数据表(PDF) 183 Page - Toshiba Semiconductor

部件名 TMP86FS49AIUG
功能描述  8 Bit Microcontroller
PDF  296 Pages
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制造商  TOSHIBA [Toshiba Semiconductor]
网页  http://www.semicon.toshiba.co.jp/eng
标志 TOSHIBA - Toshiba Semiconductor

TMP86FS49AIUG 数据表(HTML) 183 Page - Toshiba Semiconductor

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Page 167
TMP86FS49AIUG
Figure 14-7 Exaple of External Clock and MSB Transmit Mode
Figure 14-8 Hold Time of the End of Transmit Mode
(4)
Transmit error processing
Transmit errors occur on the following situation.
• Shift operation starts before writing next transmit data to SIO1TDB in external clock opera-
tion.
If transmit errors occur during transmit operation, SIO1SR<TXERR> is set to “1” immedi-
ately after starting shift operation. Synchronizing with the next serial clock falling edge,
INTSIO1 interrupt request is generated.
If shift operation starts before writing data to SIO1TDB after SIO1CR<SIOS> is set to “1”,
SIO1SR<TXERR> is set to “1” immediately after shift operation is started and then
INTSIO1 interrupt request is generated.
SO1 pin is kept in high level when SIO1SR<TXERR> is set to “1”. When transmit error
occurs, transmit operation must be forcibly stop by writing SIO1CR<SIOINH> to “1”. In
this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and SIO1TDB register are
initialized.
Writing transmit
data C
Writing transmit
data B
Writing transmit
data A
C
B
A7 A6
A
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Start shift
operation
Start shift
operation
Start shift
operation
Clearing SIOS
Writing transmit data
SIO1CR<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
SCK1
pin
SO1 pin
SIO1SR<TXF>
INTSIO1
interrupt
request
SIO1TDB
4/fc
8/fc
tSODH
tSODH
<
<
SCK1
pin
SIO1SR<SIOF>
SO1 pin



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