TMP86FS49AIUG datasheet(199/296 Pages) TOSHIBA

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Page 183

TMP86FS49AIUG

(2)

LSB receive mode

LSB receive mode is selected by setting SIO2CR<SIODIR> to “1”, in which case the data is

received sequentially beginning with the least significant bit (Bit0).

15.3.2.3 Transmit/receive mode

(1)

MSB transmit/receive mode

MSB transmit/receive mode are selected by setting SIO2CR<SIODIR> to “0” in which case the

data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received

sequentially beginning with the most significant (Bit7).

(2)

LSB transmit/receive mode

LSB transmit/receive mode are selected by setting SIO2CR<SIODIR> to “1”, in which case the

data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received

sequentially beginning with the least significant (Bit0).

15.3.3 Transfer modes

Transmit, receive and transmit/receive mode are selected by using SIO2CR<SIOM>.

15.3.3.1 Transmit mode

Transmit mode is selected by writing “00B” to SIO2CR<SIOM>.

(1)

Starting the transmit operation

Transmit mode is selected by setting “00B” to SIO2CR<SIOM>. Serial clock is selected by using

SIO2CR<SCK>. Transfer direction is selected by using SIO2CR<SIODIR>.

When a transmit data is written to the transmit buffer register (SIO2TDB), SIO2SR<TXF> is

cleared to “0”.

After SIO2CR<SIOS> is set to “1”, SIO2SR<SIOF> is set synchronously to “1” the falling edge of

SCK2

pin.

The data is transferred sequentially starting from SO2 pin with the direction of the bit specified by

SIO2CR<SIODIR>, synchronizing with the SCK2 pin's falling edge.

SIO2SR<SEF> is kept in high level, between the first clock falling edge of SCK2 pin and eighth

clock falling edge.

SIO2SR<TXF> is set to “1” at the rising edge of pin after the data written to the SIO2TDB is

transferred to shift register, then the INTSIO2 interrupt request is generated, synchronizing with the

next falling edge on SCK2 pin.

Note 1: In internal clock operation, when SIO2CR<SIOS> is set to "1", transfer mode does not start

without writing a transmit data to the transmit buffer register (SIO2TDB).

Note 2: In internal clock operation, when the SIO2CR<SIOS> is set to "1", SIO2TDB is transferred to

shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from

SCK2

pin.

Note 3: In external clock operation, when the falling edge is input from SCK2 pin after SIO2CR<SIOS> is

set to "1", SIO2TDB is transferred to shift register immediately.

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