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TMP86FS49AIUG 数据表(PDF) 202 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 202 Page - Toshiba Semiconductor |
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202 / 296 page  Page 186 15. Synchronous Serial Interface (SIO2) 15.3 Function TMP86FS49AIUG Figure 15-9 Example of Transmit Error Processingme 15.3.3.2 Receive mode The receive mode is selected by writing “01B” to SIO2CR<SIOM>. (1) Starting the receive operation Receive mode is selected by setting “01” to SIO2CR<SIOM>. Serial clock is selected by using SIO2CR<SCK>. Transfer direction is selected by using SIO2CR<SIODIR>. After SIO2CR<SIOS> is set to “1”, SIO2SR<SIOF> is set synchronously to “1” the falling edge of SCK2 pin. Synchronizing with the SCK2 pin's rising edge, the data is received sequentially from SI2 pin with the direction of the bit specified by SIO2CR<SIODIR>. SIO2SR<SEF> is kept in high level, between the first clock falling edge of SCK2 pin and eighth clock falling edge. When 8-bit data is received, the data is transferred to SIO2RDB from shift register. INTSIO2 inter- rupt request is generated and SIO2SR<RXF> is set to “1” Note: In internal clock operation, when the SIO2CR<SIOS> is set to "1", the serial clock is generated from SCK2 pin after maximum 1-cycle of serial clock frequency. (2) During the receive operation The SIO2SR<RXF> is cleared to “0” by reading a data from SIO2RDB. In the internal clock operation, the serial clock stops to “H” level by an automatic-wait function when the all of the 8-bit data has been received. Automatic-wait function is released by reading a received data from SIO2RDB. Then, receive operation is restarted after maximum 1-cycle of serial clock. In external clock operation, after SIO2SR<RXF> is set to “1”, the received data must be read from SIO2RDB, before the next data shift-in operation is finished. Writing transmit data B Writing transmit data A Unknown B A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Start shift operation Start shift operation Start shift operation SIO2CR<SIOS> SIO2SR<SIOF> SIO2SR<SEF> SCK2 pin SO2 pin SIO2SR<TXF> SIO2SR<TXERR> INTSIO2 interrupt request SIO2TDB SIO2CR <SIOINH> |
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