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TMP86FS49AIUG 数据表(PDF) 205 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 205 Page - Toshiba Semiconductor |
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205 / 296 page  Page 189 TMP86FS49AIUG Figure 15-12 Example of Receive Error Processing Note: If receive error is not corrected, an interrupt request does not generate after the error occurs. 15.3.3.3 Transmit/receive mode The transmit/receive mode are selected by writing “10” to SIO2CR<SIOM>. (1) Starting the transmit/receive operation Transmit/receive mode is selected by writing “10B” to SIO2CR<SIOM>. Serial clock is selected by using SIO2CR<SCK>. Transfer direction is selected by using SIO2CR<SIODIR>. When a transmit data is written to the transmit buffer register (SIO2TDB), SIO2SR<TXF> is cleared to “0”. After SIO2CR<SIOS> is set to “1”, SIO2SR<SIOF> is set synchronously to the falling edge of SCK2 pin. The data is transferred sequentially starting from SO2 pin with the direction of the bit specified by SIO2CR<SIODIR>, synchronizing with the SCK2 pin's falling edge. And receiving operation also starts with the direction of the bit specified by SIO2CR<SIODIR>, synchronizing with the SCK2 pin's rising edge. SIO2SR<SEF> is kept in high level between the first clock falling edge of SCK2 pin and eighth clock falling edge. SIO2SR<TXF> is set to “1” at the rising edge of SCK2 pin after the data written to the SIO2TDB is transferred to shift register. When 8-bit data has been received, the received data is transferred to SIO2RDB from shift register, then the INTSIO2 interrupt request occurs, synchronizing with setting SIO2SR<RXF> to “1”. Note 1: In internal clock operation, when the SIO2CR<SIOS> is set to "1", SIO2TDB is transferred to shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from SCK2 pin. Note 2: In external clock operation, when the falling edge is input from SCK2 pin after SIO2CR<SIOS> is set to "1", SIO2TDB is transferred to shift register immediately. When the rising edge is input from SCK2 pin, receive operation also starts. Reading received data B Reading received data A B A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 Start shift operation Start shift operation Start shift operation Write a "0" after reading the received data when a receive error occurs. SIO2CR<SIOS> SIO2SR<SEF> SCK2 pin SIO2SR<RXERR> INTSIO2 interrupt request SIO2RDB SI2 pin SIO2SR<SIOF> SIO2SR<RXF> |
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