ST40RA datasheet(72/94 Pages) STMICROELECTRONICS

72 / 94 page

ADCS 7260755H

STMicroelectronics

72/94

ST40RA

8 Pin description

8.4

Pin states

The following table shows the direction and state of the pins during and immediately after reset.

Z indicates an output or I/O pin that has been tri-stated.

I indicates an input or I/O pin in input modes (I/O buffer tri-stated).

1 indicates an output or I/O pin driving logical high.

0 indicates an output or I/O pin driving logical low.

X indicates an output or I/O pin driving undefined data.

H indicates a pin with weak internal pull-up enabled.

L indicates a pin with weak internal pull-down enabled.

Pin names

Architecturally defined

reset state

Implementation reset state during and after

reset

Dir

During reset

Dir

During reset

Following reset

LMI system pins

LDATA0:63

I/O

LBANK0:1

I/O

LADDR0:14

I/O

1...1

LDQS0:7

I/O

LCLKOUTA:B

I/O

NOTLCLKOUTA:B

I/O

LDQM0:7

I/O

NOTLCSA/B0:1,

I/O

NOTLRASA:B,

NOTLCASA:B, NOTLWEA:B

I/O

LCLKEN0:1

I/O

PCI system pins

PAD0:31

I/O

NOTPCBE0:3

I/O

PPAR

I/O

NOTPFRAME

I/O

NOT PIRDY

I/O

NOTPTRDY

I/O

NOTPSTOP

I/O

NOTPERR

I/O

NOTPSERR

I/O

NOTPDEVSEL

I/O

PIDSEL

I/O

NOTPRST

I/O

Table 36: Pin reset states for ST40RA

ST40RA 数据表(PDF) 72 Page - STMicroelectronics

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