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ST40RA 数据表(PDF) 86 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 86 Page - STMicroelectronics |
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86 / 94 page  ADCS 7260755H STMicroelectronics 86/94 ST40RA A Interconnect architecture [23:16] PCI_LATENCY Defines maximum accepted latency for PCI Reset: 0x00 RW [31:24] Reserved PER_LATENCY_EMPI Peripheral arbiter: EMPI intitiator priority and latency 0x428 [3:0] EMPI_PRIORITY Defines priority for EMPI Reset: 0x1 RW [15:4] Reserved [23:16] EMPI_LATENCY Defines maximum accepted latency for EMPI Reset: 0x00 RW [31:24] Reserved PER_LATENCY_GPDMA Peripheral arbiter: GPDMA intitiator priority and latency 0x430 [3:0] GPDMA_PRIORITY Defines priority for GPDMA Reset: 0x0 RW [15:4] Reserved [23:16] GPDMA_LATENCY Defines maximum accepted latency for GPDMA Reset: 0x00 RW [31:24] Reserved PER_LATENCY_PCI Peripheral arbiter: PCI intitiator priority and latency 0x420 |
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