ST40RA datasheet(37/94 Pages) STMICROELECTRONICS

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6 Clock generation

ST40RA

37/94

STMicroelectronics

ADCS 7260755H

6.4.1

Programming the PLL output frequency

The three dividers used within the PLL are referred to as M (predivider), N (feedback divider) and P

(postdivider) for brevity. Note that there is a divide-by-2 fixed prescaler before the feedback divider.

The binary values applied to the programmable dividers, and the frequency of CLOCKIN controls

the output frequency of the PLL macrocell:

where the values of M, N and P must satisfy the following constraints:

Divider limits:

Phase comparator limits:

VCO limit:

M divider limit:

For example, if 300 MHz from an input clock of 33 MHz is to be generated, the values of M, N and

P are worked out as below.

The phase comparator must operate between 1 MHz and 2 MHz, so choose M = 22 (for

1.5 MHz operation).

The VCO needs to run between 200 MHz and 622 MHz. It could be run at 300 MHz directly

(which takes a little less current), or at 600 MHz then divide by 2 to ensure an exact 50% duty

cycle. In this example 600 MHz is chosen so N = 200.

The postdivider then needs to be a divide by 2. This is programmed in powers of 2, so P = 1.

The P divider changes value without glitching of the output clock.

6.4.2

Changing clock frequency

The clock frequencies are changed in two ways.

Change the core PLL frequencies.

The PLL must be stopped, the control register reconfigured with the new settings, and the PLL

restarted at the new frequency.

Change the frequency division ratio of the clock domains.

The control registers are changed dynamically and the new frequencies are effective

immediately.

6.4.3

Changing the core PLL frequencies

This procedure applies to either CLOCKGENA or CLOCKGENB and to PLL1 or PLL2.

Stop the PLL. The CLOCKGENA.PLL1CR2.STBPLLENSEL register selects whether the PLL

is enabled by the CLOCKGENA.PLL1CR2.STBPLLEN or the CPG.FRQCR.PLL1EN register.

Reconfigure the PLL. Set the CLOCKGENA.PLL1CR1 register to one of the supported

configurations on the datasheet.

Restart the PLL, following the procedure described in the

ST40 System Architecture Volume 1:

System.

F clockout

()

M2P

------------------

F clockin

()

255 1

255 0

≤≤

1MHz

F clockin

()

-----------------------------

2MHz

≤≤

200MHz

-------------



 F clockin

()

622MHz

≤≤

F clockin

() 200MHz·

≤

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