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ST40RA 数据表(PDF) 27 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 94 page ![]() 5 System configuration ST40RA 27/94 STMicroelectronics ADCS 7260755H 5.9.4.2 SYSCONF.SYS_CON1 . Where the two clocks are sourced from independent PLLs the bridge must be put in asynchronous mode. 5.9.5 SYSCONF.SYS_CON2. SYSCONF.SYS_CON1 Memory bridge control 0x010 [3:0] Reserved RW [10:4] MB1 Memory bridge 1 control: EMI target RW [17:11] MB2 Memory bridge 2 control: EMPI initiator RW [24:18] MB3 Memory bridge 3 control: EMI_SS target RW [38:25] Reserved [45:39] MB6 Memory bridge 6 control: PCI initiator RW [52:46] MB7 Memory bridge 7 control: PCI target RW [63:53] Reserved SYSCONF.SYS_CON2 Functional pin use and behavior 0x0018 The SYSCONF.SYS_CON2 register controls functional pin use and behavior 8LMI_MODE LMI pad type 0: SSTL 1: LVTTL Reset: 0 RW 9 LMI_ENVREF Reference voltage source 0: internally generated reference voltage 1: external reference voltage from VREF pins Reset: 0 RW 10 LMI_ECLK_BYPASS LMI control signal ECLK180 retime bypass 0: ECLK180 flip flop not bypassed 1: ECLK180 flip flop is bypassed Reset: 0 RW 11 LMI_NOTCOMP25_EN Enable LMI 2.5 V compensation cell 0: LMI 2.5 V compensation cell enabled 1: LMI 2.5 V compensation cell disabled Reset: 0 RW 12 LMI_COMP33_EN Enable LMI 3.3 V compensation cell 0: LMI 2.5 V compensation cell enabled 1: LMI 2.5 V compensation cell disabled Reset: 0 RW |
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