ST40RA datasheet(50/94 Pages) STMICROELECTRONICS

50 / 94 page

ADCS 7260755H

STMicroelectronics

50/94

ST40RA

7 Electrical specifications

7.3

PCI interface AC specifications

Figure 10: PCI timings

Symbol

Parameter

Min

Max

Units

Note

tPCIHPCIH

PCI clock period

a. Specified with 30 pF load

tPCIHAOV

PCLK high to all PCI output signals valid

a, b

b. Need to use 4 ns of the PCI propagation delay

tPCIHAOZ

PCLK high to all PCI outputs tri-state

tPCIHAON

PCLK high to all PCI outputs on

tBIVPCIH

Bused input signals valid to PCLK high

c. NOTPREQ[0:3] and NOTPGNT[0:3] are point to point signals and have different input setup times

to bussed signals. All other synchronous signals are bussed.

tPIVPCIH

Point-to-point input signals valid to PCLK high

tPCIHAIX

All PCI input signals hold after PCLK high

Table 25: PCI AC timings

Tri-state outputs

PCLK

Outputs

tPCIHAOV

tPCIHAON

tPCIHAOZ

Inputs: bussed

tPCIHAIX

tBIVPCIH

Inputs: point-to-point

tPIVPCIH

tPCIHPCIH

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