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ST40RA 数据表(PDF) 34 Page - STMicroelectronics

部件名 ST40RA
功能描述  32-bit Embedded SuperH Device
PDF  94 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST40RA 数据表(HTML) 34 Page - STMicroelectronics

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ST40RA
6 Clock generation
6.2
Recommended operating modes
6.3
Clocks and registers at start up
Mode for
CLOCKGENA and
CLOCKGENB
PLL
frequency
(MHz)
ST40RA clock domain frequencies (MHz)
PLLA
(mode)
PLLB
(mode)
PLLA
PLLB
CPU_
CLK
STBUS_
CLK
PER_
CLK
LMI_
CLK
EMI_SS_
CLK
PCI_SS_
CLK
Recommended reset configuration
0
-
200
-
100
50
25
50
50
50
Alternate reset configuration
1
-
266
-
133
88
44
88
88
88
2
-
300
-
150
100
50
100
100
100
3
-
332
-
166
111
66
111
111
111
Recommended operating modes
2
-
300
-
150
100
100
100
100
100
3
-
332
-
166
83
83
83
83
83
Low power configuration with clocks enabled (programmable after reset)
A6
bypass
-
27
-
13.5
6.75
6.75
6.75
6.75
6.75
Table 14: Supported operating frequencies
Reset
mode
Reset
mode
MODE[2:0]
CLOCKGENA
.PLL1CR1
reset value
CLOCKGENA
core
frequency
(PLL1)
fPLL/2
CLK1
CPU_
CLK
CLK2
STBUS_
CLK
CLK3
PER_
CLK
CLK4
LMI_
CLK
0
000
0x7939 8612
200 MHz
100
1
1/2
1/4
1/2
1
001
0x7939 B112
266 MHz
133
1
2/3
1/3
2/3
2
010
0x7938 6412
300 MHz
150
1
2/3
1/3
2/3
3
011
0x7938 7B14
332 MHz
166
1
2/3
1/3
2/3
4
100
0x7938 8612
400 MHz
200
1
1/2
1/4
1/2
5
101
0x7938 A712
500 MHz
250
1
1/2
1/4
1/2
6
110
0x0938 0000
0 MHz
0
1
1/2
1/2
1/2
7
111
0x0939 8612
200 MHz
100
1/2
1/4
1/4
1/4
Table 15: CLOCKGENA PLL1 reset values



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