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ST40RA 数据表(PDF) 82 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 94 page  ADCS 7260755H STMicroelectronics 82/94 ST40RA A Interconnect architecture A.2.2 LMI2 arbiter [23:16] NODE2_LATENCY Defines maximum accepted latency for node 2 initiators Reset: 0x00 RW [31:24] Reserved LATENCY_LMI2_ENABLE LMI2 arbiter: enable latency counters 0x110 0 Reserved Reset: Always 0 1 ENABLE_PCI Enable latency check for PCI Reset: 0 RW 2 ENABLE_EMPI Enable latency check for EMPI Reset: 0 RW 3 ENABLE_GPDMA Enable latency check for GPDMA Reset: 0 RW [31:4] Reserved Reset: Always 0 LMI2_CPU_PRI LMI2 arbiter: CPU priority 0x118 [3:0] CPU_PRIORITY Defines priority for CPU Reset: 0x0 RW [31:4] Reserved LMI2_LATENCY_PCI LMI2 arbiter: PCI intitiator priority and latency 0x120 [3:0] PCI_PRIORITY Defines priority for PCI Reset: 0x3 RW [15:4] Reserved [23:16] PCI_LATENCY Defines maximum accepted latency for PCI Reset: 0x00 RW [31:24] Reserved LMI2_LATENCY_EMPI LMI2 arbiter: EMPI intitiator priority and latency 0x128 [3:0] EMPI_PRIORITY Defines priority for EMPI Reset: 0x2 RW [15:4] Reserved [23:16] EMPI_LATENCY Defines maximum accepted latency for EMPI Reset: 0x00 RW [31:24] Reserved LATENCY_LMI1_VALUE LMI1 arbiter: node 2 intitiator priority and latency 0x020 |
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