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ST40RA 数据表(PDF) 32 Page - STMicroelectronics

部件名 ST40RA
功能描述  32-bit Embedded SuperH Device
PDF  94 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST40RA 数据表(HTML) 32 Page - STMicroelectronics

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ST40RA
6 Clock generation
The sources for PCI_SS_CLK and EMI_SS_CLK, can be set using the PCI_SEL and EMI_SEL bits
in the CLOCKGENB.CLK_SELCR register. See
Section 6.6.1: CLOCKGENB.CLK_SELCR register
on page 39.
If CLOCKGEN_A13 is used as PCI_SS_CLK source then the memory bridges 6 and 7 must be
enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass mode. This is the
recommended mode of operation.
If either CLOCKGEN_B12 or CLOCKGEN_A14 are used as the EMI_CLK, the memory bridges 1, 2
and 3 must be enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass.
This is the recommended mode of operation.
See
Chapter 5.8: Memory bridge control on page 21.
Subsystem
Clock domain
Target frequencies
(MHz)
Sourcea
Ratio
CPU core
CPU_CLK
200
166
150
133
CLOCKGEN_A11
1
SuperHyway
STBUS_CLK
-
111
100
88
CLOCKGEN_A12
2/3
100
83
75
67
1/2
Peripherals
PER_CLK
(CPU core PCK)
-
5550
44CLOCKGEN_A13
1/3
50
42
38
33
1/4
PCI bus clock
PCI_BUS_CLK
33
CLOCKGEN_A21
1/16
66
CLOCKGEN_A22
1/8
25.14
CLOCKGEN_A23
1/21
Disabled
CLOCKGEN_A24
-
PCI subsystem
PCI_SS_CLK
-
111
100
88
CLOCKGEN_A12
2/3
100
83
75
67
1/2
-
5550
44CLOCKGEN_A13
1/3
50
42
38
33
1/4
Local memory
interface (LMI)
LMI_CLK
133
111
100
88
CLOCKGEN_A14
2/3
Reserved
CLOCKGEN_B11
1
EMI subsystem
EMI_CLK
50 to 100 MHz
CLOCKGEN_B12
1
-
111
100
88
CLOCKGEN_A12
2/3
100
83
75
67
CLOCKGEN_A14
1/2
Table 13: Clock domains
a. Clock naming: CLOCKGEN_[CLOCKGEN label][PLL number][clock number]



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