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ST40RA 数据表(PDF) 73 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 94 page ![]() 8 Pin description ST40RA 73/94 STMicroelectronics ADCS 7260755H NOTPLOCK I - I/O H PCLK I - I/O Z NOTPREQ[0:3] I - I/O Z NOTPGNT[0:3] O 1 I/O 1111 PCLKOUT O Running I/O Running NOTPINTA I/O - I/O H GPDMA pins DACK0, DACK1 O Z I/O 0 DRAK0, DRAK1 O Z I/O 0 DREQ0, DREQ1 I - I/O Z Serial communication interface with FIFO (SCIF) pins SCI2 I - I/O H CTS1 O Z I/O H RXD0, RXD1 I - I/O H SCK0, SCK1 I - I/O H TXD0, TXD1 O Z I/O H Power, clocks and so on NOTRST I - I (0) (1) IRL0:3, NMI I - I H TMUCLK I/O - I/O H LPCLKIN I - I 0 CLKIN I - I Running LPCLKOSC, CLKOSC O Oscillator output O Running AUXCLKOUT O CLKIN O CLKIN STATUS1:0 O 11 O 11 00 AUDATA0:3 O 00 O 0000 AUDSYNC O 1 O 1 AUDCLK O 0 O 0 NOTASEBRK I - I/O (1) DCLK, TCK, EADDR,TDI I - I (0) NOTTRST, I - I (0) (1) TDO O Z O Z Pin names Architecturally defined reset state Implementation reset state during and after reset Dir During reset Dir During reset Following reset Table 36: Pin reset states for ST40RA |
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