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ST40RA 数据表(PDF) 89 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 94 page ![]() B Implementation restrictions ST40RA 89/94 STMicroelectronics ADCS 7260755H B.6 PIO B.6.1 PIO default functionality following reset In the ST40 family device, the operational modes for these registers differ from the standard architecture definition and are shown in Table 39. B.6.2 PCI/PIO alternate functions The following PIO signals cannot be used when PCI is enabled even if the PCI implementation does not require the primary pin function. If PCI is disabled, the alternate functions may be used. PIO bit configuration PIO output state PIO.PC2 PIO.PC1 PIO.PC0 NonPIO functiona a. State following reset -0 0 0 PIO bidirectional Open drain 0 0 1 PIO output Push-pull 0 1 0 PIO bidirectional Open drain 0 1 1 PIO input High impedance 1 0 0 PIO input High impedance 1 0 1 Reserved - 1 1 0 Reserved - 1 1 1 Table 39: PIO alternate function registers Pin name BPN Architecture signal name Pin function Pin Row Col Default Alternate Type Dir NOTPREQ0 E 18 NOTPCI_REQ0 PCI external request for bus PIO16 P8 I/O I/O NOTPREQ1 E 17 NOTPCI_REQ1 PCI external request for bus PIO18 P8 I I/O NOTPREQ2 F 16 NOTPCI_REQ2 PCI external request for bus PIO20 P8 I I/O NOTPREQ3 G 16 NOTPCI_REQ3 PCI external request for bus PIO22 EMPIDREQ1 P8 I I/O O Table 40: PCI/PIO alternate functions |
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