ST40RA datasheet(80/94 Pages) STMICROELECTRONICS

80 / 94 page

ADCS 7260755H

STMicroelectronics

80/94

ST40RA

A Interconnect architecture

A.1.5

LMI2 arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) as to be to work fixed priority mode in the following priority

order:

PCI,

EMPI,

GPDMA,

CPU buffer (although the CPU requests are not supposed to go in that node to be send in the

LMI, it has to be managed in order to avoid deadlock).

The priority order have to be programmable and the latency checking algorithm can be enabled for

GPDMA, PCI, EMPI.

A.1.6

Return arbitration

The possibilities of the return arbitration are simpler than for the request arbitration. The arbiter is

not programmable but a specific arbitration can be chosen when implementing it.

The arbitration mode chosen is the fixed priority. For each arbiter (one per initiator), the order is the

following: LMI then other targets for the arbiters in node 1 and LMI, EMI, PCI, peripheral subsystem

for the arbiters of node 2.

A.2

Interconnect registers

A summary of registers is given in

Table 38. Addresses in the table are offset from the interconnect

base address at 0x1B05 0000.

Address

offset

Name

Function

0x010

LATENCY_LMI1_ENABLE

Enables or disables initiators latency counters, see

LMI1 arbiter on page 81

0x018

LMI1_CPU_PRI

Defines priority for the CPU in the LMI1 arbiter, see

LMI1 arbiter on page 81

0x020

LATENCY_LMI1_VALUE

Defines priority and latency value for the node 2 in the LMI1 arbiter, see

LMI1 arbiter on page 81

0x110

LATENCY_LMI2_ENABLE

Enables or disables initiators latency counters, see

LMI2 arbiter on page 82

0x118

LMI2_CPU_PRI

Defines priority for the CPU in the LMI2 arbiter, see

LMI2 arbiter on page 82

0x120

LMI2_LATENCY_PCI

Defines priority and latency value for PCI initiator in the PCI arbiter, see

LMI2 arbiter on page 82

0x128

LMI2_LATENCY_EMPI

Defines priority and latency value for EMPI initiator in the PCI arbiter, see

LMI2 arbiter on page 82

0x130

LMI2_LATENCY_GPDMA

Defines priority and latency value for GPDMA initiator in the PCI arbiter,

see

LMI2 arbiter on page 82

0x210

LATENCY_EMI_ENABLE

Enables or disables initiators latency counters, see

EMI arbiter on page 83

0x218

EMI_CPU_PRI

Defines priority for the CPU in the EMI arbiter, see

EMI arbiter on page 83

0x220

EMI_LATENCY_PCI

Defines priority and latency value for PCI initiator in the EMI arbiter, see

EMI arbiter on page 83

0x228

EMI_LATENCY_EMPI

Defines priority and latency value for EMPI initiator in the EMI arbiter, see

EMI arbiter on page 83

Table 38: Interconnect register summary

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