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ST40RA 数据表(PDF) 53 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 94 page  7 Electrical specifications ST40RA 53/94 STMicroelectronics ADCS 7260755H 7.6 DDR bus termination (SSTL_2) The JEDEC specification for SSTL_2 and an application note from a DDR SDRAM manufacturer (DDR SDRAM Signaling Design Notes (MIcron Technology)) recommend the following layout to reduce signal reflections on the bus: tLCLLCH LMI clock low period 0.45 tLCHLCH tLCHLAV LCLKOUT low to address and command valid -1.5 1.5 ns tLCHDQSR LCLKOUT high to read DQS edge -1.5 1.5 ns a tDQSH DQS high 0.45 tLCHLCH tDQSL DQS low 0.45 tLCHLCH tDQSRS Read data setup for DQS edge 1 - tLCHLCH / 4 ns a tDQSRH Read data hold for DQS edge tLCHLCH / 4 + 1 ns a tLCHDQS LCLKOUT high to write DQS N * tLCHLCH / 4 - 0.75 N * tLCHLCH / 4 + 0.75 ns tLDWS Write data setup to DQS edge N * tLCHLCH / 4 - 0.75 ns tLDWH DQS edge to Write data invalid N * tLCHLCH / 4 + 0.75 ns tLCHDWZ LCLKOUT high to write data Z 2 ns a. Constraint placed on external system Figure 13: SSTL_2 bus termination Symbol Parameter Min Max Units Note Table 27: LMI DDR-SDRAM AC timings RS DDR DDR RS RS RT VTT VTT = 1.25 V (VDD / 2) RS = 27 Ω RT = 27 Ω |
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