ST40RA datasheet(30/94 Pages) STMICROELECTRONICS

30 / 94 page

ADCS 7260755H

STMicroelectronics

30/94

ST40RA

6 Clock generation

5.9.7

PCI.PERF register definition.

Clock generation

The ST40 clock architecture has been organized to maintain compatibility across the ST40 family

and allow additional flexibility to increase system performance where required. It includes a more

diverse range of peripherals and provides low power use.

6.1

Clock domains and sources

Figure 4 shows possible clock domains for ST40RA clocks. The ST40RA implementation includes

two CLOCKGEN macros, which supply up to three independent clock domains across the chip

Each PLL may be independently programmed to produce a clock at a specific frequency which is

used to derive a series of related clocks which may be used by the system.

The clock domains mapping is shown in

Table 13. The architecture of the ST40RA CLOCKGEN

subsystem consists of two standard (ST40 family) CLOCKGEN units (CLOCKGENA and

CLOCKGENB) and a CLOCKCON block.

Figure 5 shows the architecture of the ST40RA

CLOCKGEN subsystem.

PCI.PERF

0x0080

PCI.PERF modifies the function of the PCI.

[3:0]

DLY_PERRSAMPLE

Parity error delay

Number of APP_CLOCK cycles after end of PCI that access master

should wait to see if there is a parity error

ENB_WRITEPOST

Enable write posting in master

ENB_STBYBYPASS

Enable standby bypass

[31:6]

Reserved

ST40RA 数据表(PDF) 30 Page - STMicroelectronics

ST40RA 数据表(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

数据表下载