ST40RA datasheet(59/94 Pages) STMICROELECTRONICS

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8 Pin description

ST40RA

59/94

STMicroelectronics

ADCS 7260755H

Pin description

8.1

Function pin use selection

Full details of the functional pin sharing are found in

Section 8.3: PBGA 27 x 27 ballout on page 61.

8.2

Mode selection

During the power-on reset cycle a range of basic system configurations can be set up with resistive

pull-ups or pull-downs. A detailed description of these selections is found in the relevant chapters of

the

ST40 System Architecture Manual.

See

Section 8.3: PBGA 27 x 27 ballout on page 61 for information on which pins these mode inputs

have been placed on the ST40RA.

Functional pin

group

Pins

Alternate use(s)

High-end interactive

set-top box (with STi5514)

example use

PCI request and

grant

NOTPREQ[0:3]

NOTPGNT[0:3]

NOTPINTA

PIO[14:23]

PCI bus

PCI request and

grant

NOTPREQ[2:3]

NOTPGNT[2:3]

PIO[14:23]

EMPIDREQ[0:1]

EMPIDACK[0:1]

PCI bus

GPDMA

handshake

DACK[0:1]

DREQ[0:1]

DRAQ[0:1]

PIO[8:13]

EMPIDREQ[2:3]

EMPIDACK[2:3]

EMPIDRACK[2:3]

GPDMA

2 x SCIF

SCI2, CTS1

RXD0, RXD1

SCK0, SCK1

TXD0, TXD1

PIO[0:7]

2 x SCIF

Table 33: ST40RA functional pin sharing summary

Mode

Pin name

Architectur

e signal

name

Block

affected

Description

Notes

MODE2:0

EADDR2

EADDR3

EADDR4

MD2:0

CLOCKGEN

Set system clock operating mode

MODE4:3

EADDR5

EADDR6

MD4:3

CLOCKGEN

Set PCI clock operating mode

MODE5

EADDR7

MD5

CLOCKGEN

Set clock input source

H: Crystal, L: External

Table 34: Mode selection pins for ST40RA

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