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ST40RA 数据表(PDF) 42 Page - STMicroelectronics |
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ST40RA 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 94 page  ADCS 7260755H STMicroelectronics 42/94 ST40RA 6 Clock generation 6.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register Table 19 defines the mapping of modules to bits in the STBREQ and STBACK registers. CLOCKGENA.STBACKCR CLOCKGENB.STBACKCR Current module power status 0x0030 This register indicates the current module power status [0:7] ACK[0:7] Power down status for module [n] Indicates the current power down status of the module [n] Bit [n]: 0 Module [n] operating normally Bit [n]: 1 Module [n] powered down Reset state: 0 RO [8:31] Reserved 0: No action 1: Undefined Reset state: Undefined Bit number CLOCKGENA mapping CLOCKGENB mapping 0EMI Reserved 1LMI Reserved 2 DMAC Reserved 3 PCI Reserved 4PIO Reserved 5 Reserved Reserved 6 Reserved PCI bus 7 Reserved Reserved Table 19: STBREQ and STBACK mapping for modules |
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