R8CSLASH2G datasheet(157/344 Pages) RENESAS

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R8C/2G Group

16. Watchdog Timer

Rev.1.00

Apr 04, 2008

Page 137 of 318

REJ09B0387-0100

16. Watchdog Timer

The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is

recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows

selection of count source protection mode enable or disable.

Table 16.1 lists information on the Watchdog Timer Specifications.

Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.

Figure 16.1 shows the Block Diagram of Watchdog Timer. Figure 16.2 shows the Registers WDTR, WDTS, and

WDC. Figure 16.3 shows the Registers CSPR and OFS.

Table 16.1

Watchdog Timer Specifications

Item

Count Source Protection

Mode Disabled

Count Source Protection

Mode Enabled

Count source

CPU clock

XCIN clock divided by 32

(fC32)

Low-speed on-chip oscillator

clock

Count operation

Decrement

Count start condition Either of the following can be selected

• After reset, count starts automatically

• Count starts by writing to WDTS register

Count stop condition Stop mode, wait mode

Stop mode

None

Reset condition of

watchdog timer

• Reset

• Write 00h to the WDTR register before writing FFh

• Underflow

Operation at the time

of underflow

Watchdog timer interrupt or watchdog timer reset

Watchdog timer reset

Select functions

• Division ratio of prescaler (when select the CPU clock as the count source)

Selected by the WDC7 bit in the WDC register

• The default value of the watchdog timer (when select fC32 as the count source)

Selected by bits CVS0 to CVS1 in the CSPR register

• Count source protection mode

Whether count source protection mode is enabled or disabled after a reset can

be selected by the CSPROINI bit in the OFS register (flash memory). If count

source protection mode is disabled after a reset, it can be enabled or disabled by

the CSPRO bit in the CSPR register (program).

• Starts or stops of the watchdog timer after a reset

Selected by the WDTON bit in the OFS register (flash memory).

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