R8CSLASH2G datasheet(160/344 Pages) RENESAS

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R8C/2G Group

16. Watchdog Timer

Rev.1.00

Apr 04, 2008

Page 140 of 318

REJ09B0387-0100

Figure 16.3

Registers CSPR and OFS

Count Source Protection Mode Register

Symbol

Address

After Reset(1)

CSPR

001Ch

00h

Bit Symbol

Bit Name

Function

NOTES:

b7 b6 b5 b4 b3 b2 b1 b0

CSPRO

Count source protection mode

select bit(4)

0 : Count source protection mode disabled

1 : Count source protection mode enabled

—

Watchdog timer default value

select bit(2)

b1 b0

0 0 : 01FFh (512)

0 1 : 03FFh (1024)

1 0 : 07FFh (2048)

1 1 : 0FFFh (4096)

Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.

When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.

—

(b6-b3)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

When the CSPRO bit is set to 0 (count source protection mode disabled), the CSS bit is enabled.

When the CSS bit is set to 1 (fC32), Bits CVS0 to CVS1 are enabled.

CVS0

CVS1

CSS

Count source select bit(3)

0 : CPU clock

1 : fC32

Option Function Select Register(1)

Symbol

Address

When Shipping

OFS

0FFFFh

FFh(3)

Bit Symbol

Bit Name

Function

NOTES:

3. If the block including the OFS register is erased, FFh is set to the OFS register.

—

(b6)

Reserved bit

Set to 1.

CSPROINI

Count source protect

mode after reset select

bit

0 : Count source protect mode enabled after reset

1 : Count source protect mode disabled after reset

Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0

(voltage monitor 0 reset enabled after hardw are reset).

ROMCP1

ROM code protect bit

0 : ROM code protect enabled

1 : ROM code protect disabled

ROMCR

ROM code protect

disabled bit

0 : ROM code protect disabled

1 : ROMCP1 enabled

—

(b1)

Reserved bit

Set to 1.

WDTON

Watchdog timer start

select bit

0 : Starts w atchdog timer automatically after reset

1 : Watchdog timer is inactive after reset

b7 b6 b5 b4 b3 b2 b1 b0

—

(b4)

Reserved bit

Set to 1.

The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not

w rite additions to the OFS register.

LVD0ON

Voltage detection 0

circuit start bit(2)

0 : Voltage monitor 0 reset enabled after hardw are

reset

1 : Voltage monitor 0 reset disabled after hardw are

reset

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