R8CSLASH2G datasheet(161/344 Pages) RENESAS

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R8C/2G Group

16. Watchdog Timer

Rev.1.00

Apr 04, 2008

Page 141 of 318

REJ09B0387-0100

16.1

Count Source Protection Mode Disabled

The count source of the watchdog timer is either the CPU clock or the XCIN clock divided by 32 (fC32) can be

selected when count source protection mode is disabled. fC32 does not stop in wait mode, the watchdog timer to

count continues.

Table 16.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).

NOTES:

1. The watchdog timer is reset when 00h is written to the WDTR register before FFh.

2. The prescaler is reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused

by the prescaler.

3. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh

with a flash programmer.

Table 16.2

Watchdog Timer Specifications (with Count Source Protection Mode Disabled)

Item

Specification

Count source

CPU clock

XCIN clock divided by 32 (fC32)

Count operation Decrement

Period

count value of watchdog

timer (32768)(1, 2)

count value of watchdog timer (m)(1)

n: 16 or 128 (selected by WDC7 bit in WDC

Example: When the CPU clock frequency is 8 MHz

and prescaler divided by 16, the period is

approximately 65.5 ms

m: 512, 1024, 2048 or 4096 (selected by bits

CVS0 to CVS1 in the CSPR register)

Example: When the XCIN clock frequency is

32.768 kHz and the count value by

512, the period is 0.5 s

Reset condition

of watchdog

timer

•Reset

• Write 00h to the WDTR register before writing FFh

• Underflow

Count start

condition

The WDTON bit(3) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a

reset

• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset)

The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register

is written to

• When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting)

The watchdog timer and prescaler start counting automatically after a reset

Count stop

condition

Stop and wait modes (inherit the count from the

held value after exiting modes)

Stop mode (inherit the count from the held

value after exiting modes)

Operation at

time of

underflow

• When the PM12 bit in the PM1 register is set to 0

Watchdog timer interrupt

• When the PM12 bit in the PM1 register is set to 1

Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)

Division ratio of prescaler (n)

CPU clock

----------------------------------------------------------------------------

XCIN clock

-----------------------------

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