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数据搜索系统，热门电子元器件搜索 |
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R8C/2G 数据表(PDF) 158 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 158 Page - Renesas Technology Corp |
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158 / 344 page  R8C/2G Group 16. Watchdog Timer Rev.1.00 Apr 04, 2008 Page 138 of 318 REJ09B0387-0100 Figure 16.1 Block Diagram of Watchdog Timer Internal reset signal Write to WDTR register Set to default value(1) PM12 = 1 Watchdog timer reset PM12 = 0 Watchdog timer interrupt request CSS, CSPRO: Bits in CSPR register WDC7: Bit in WDC register PM12: Bit in PM1 register NOTE: 1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set. When the CSPRO bit is set to 0 (count source protection mode disabled), the initial value depends on the settings of bits CVS0, CVS1, and CSS in the CSPR register. CSPRO = 0 CSPRO = 1 Watchdog timer CPU clock fOCO-S CSS = 0 CSS = 1 fC32 1/16 1/128 WDC7 = 0 WDC7 = 1 Prescaler |
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