R8CSLASH2G datasheet(159/344 Pages) RENESAS

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R8C/2G Group

16. Watchdog Timer

Rev.1.00

Apr 04, 2008

Page 139 of 318

REJ09B0387-0100

Figure 16.2

Registers WDTR, WDTS, and WDC

Watchdog Timer Reset Register

CSPRO

CSS

CVS1

CVS0

7FFFh

0100

01FFh

0101

03FFh

0110

07FFh

0111

0FFFh

1(2)

0FFFh

X: 0 or 1

NOTES:

Do not generate an interrupt betw een w hen 00h and FFh are w ritten.

When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),

0FFFh is set in the w atchdog timer.

Function

When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)

The w atchdog timer initial value depends on the CSPR register setting.

CSPR register

Default value

After Reset

WDTR

000Dh

Undefined

Symbol

Address

Watchdog Timer Control Register

Symbol

Address

After Reset

WDC

000Fh

00X11111b

Bit Symbol

Bit Name

Function

b3 b2 b1 b0

High-order bits of w atchdog timer

—

(b4-b0)

—

(b5)

b7 b6 b5 b4

Reserved bit

Set to 0. When read, the content is undefined.

WDC7

—

(b6)

Reserved bit

Set to 0.

Prescaler select bit

0 : Divide-by-16

1 : Divide-by-128

Watchdog Timer Start Register

Symbol

Address

After Reset

WDTS

000Eh

Undefined

Function

The w atchdog timer starts counting after a w rite instruction to this register.

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