HD64F2149YV datasheet(349/1075 Pages) RENESAS

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Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 321 of 1044

REJ09B0280-0300

Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed

(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,

however, and cannot be set by software.

Bit 1

OVF

Description

[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF

(Initial value)

[Setting condition]

When FRC changes from H'FFFF to H'0000

Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-

match A (when the FRC and OCRA values match).

Bit 0

CCLRA

Description

FRC clearing is disabled

(Initial value)

FRC is cleared at compare-match A

11.2.8

Timer Control Register (TCR)

Bit

Initial value

Read/Write

IEDGA

R/W

IEDGB

R/W

IEDGC

R/W

IEDGD

R/W

BUFEA

R/W

CKS0

R/W

BUFEB

R/W

CKS1

R/W

TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture

signals, enables the input capture buffer mode, and selects the FRC clock source.

TCR is initialized to H'00 by a reset and in hardware standby mode

Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A

signal (FTIA).

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