HD64F2149YV datasheet(100/1075 Pages) RENESAS

100 / 1075 page

Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 72 of 1044

REJ09B0280-0300

stop mode permits halting of the operation of individual modules, other than the CPU. Subactive

mode, subsleep mode, and watch mode are power-down modes that use subclock input. For

details, refer to section 24, Power-Down State.

Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the

software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the

low-power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop

immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.

Software Standby Mode: A transition to software standby mode is made if the SLEEP

instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR

and the PSS bit in the WDT1 timer control/status register (TCSR) are both cleared to 0. In

software standby mode, the CPU and clock halt and all MCU operations stop. As long as a

specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The

I/O ports also remain in their existing states.

Hardware Standby Mode: A transition to hardware standby mode is made when the

STBY pin

goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The

on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM

contents are retained.

2.9

Basic Timing

2.9.1

Overview

The CPU is driven by a system clock, denoted by the symbol

φ. The period from one rising edge

φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or

three states. Different methods are used to access on-chip memory, on-chip supporting modules,

and the external address space.

2.9.2

On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows

the pin states.

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