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HD64F2149YV 数据表(PDF) 32 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 32 Page - Renesas Technology Corp |
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32 / 1075 page ![]() Section 1 Overview Rev. 3.00 Jan 18, 2006 page 4 of 1044 REJ09B0280-0300 Item Specifications Serial communi- cation interface (SCI: 2 channels, SCI0, SCI1) • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function SCI with IrDA: 1 channel (SCI2) • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function • Conforms to IrDA standard version 1.0 • IrDA format encoding/decoding of TxD and RxD Keyboard buffer controller (PS2: 3 channels) • Conforms to PS/2 interface • Direct manipulation of transmission output by software • Receive data input to 8-bit shift register • Data/receive/completed interrupt, parity error detection, stop bit monitoring Host interface (HIF:XBS) • 8-bit host interface (ISA/X-BUS) port • Five host interrupt requests (HIRQ11, HIRQ1, HIRQ12, HIRQ3, HIRQ4) • Normal and fast A20 gate output • Four register sets (each comprising two data registers and a status register) Host interface (HIF:LPC) • Single-channel LPC port XBS three register set equivalence, plus 16 two-way register bytes • Seven serial host interrupt requests (SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12) • Normal and fast A20 gate output • Three register sets (each comprising two data registers and a status register) Keyboard controller • Matrix keyboard control using keyboard scan with wakeup interrupt and sense port configuration |
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