HD64F2149YV datasheet(14/1075 Pages) RENESAS

14 / 1075 page

Rev. 3.00 Jan 18, 2006 page xiv of xxviii

Section 6 Bus Controller ................................................................................................... 139

6.1

Overview........................................................................................................................... 139

6.1.1

Features................................................................................................................ 139

6.1.2

Block Diagram ..................................................................................................... 140

6.1.3

Pin Configuration................................................................................................. 141

6.1.4

6.2

Register Descriptions ........................................................................................................ 142

6.2.1

Bus Control Register (BCR) ................................................................................ 142

6.2.2

Wait State Control Register (WSCR) .................................................................. 143

6.3

Overview of Bus Control .................................................................................................. 145

6.3.1

Bus Specifications................................................................................................ 145

6.3.2

Advanced Mode ................................................................................................... 146

6.3.3

Normal Mode....................................................................................................... 146

6.3.4

I/O Select Signal .................................................................................................. 147

6.4

Basic Bus Interface ........................................................................................................... 148

6.4.1

Overview.............................................................................................................. 148

6.4.2

Data Size and Data Alignment............................................................................. 148

6.4.3

Valid Strobes........................................................................................................ 150

6.4.4

Basic Timing........................................................................................................ 151

6.4.5

Wait Control ........................................................................................................ 159

6.5

Burst ROM Interface......................................................................................................... 161

6.5.1

Overview.............................................................................................................. 161

6.5.2

Basic Timing........................................................................................................ 161

6.5.3

Wait Control ........................................................................................................ 163

6.6

Idle Cycle .......................................................................................................................... 163

6.6.1

Operation ............................................................................................................. 163

6.6.2

Pin States in Idle Cycle ........................................................................................ 164

6.7

Bus Arbitration.................................................................................................................. 165

6.7.1

Overview.............................................................................................................. 165

6.7.2

Operation ............................................................................................................. 165

6.7.3

Bus Transfer Timing ............................................................................................ 166

Section 7 Data Transfer Controller................................................................................. 167

7.1

Overview........................................................................................................................... 167

7.1.1

Features................................................................................................................ 167

7.1.2

Block Diagram ..................................................................................................... 168

7.1.3

7.2

Register Descriptions ........................................................................................................ 170

7.2.1

DTC Mode Register A (MRA) ............................................................................ 170

7.2.2

DTC Mode Register B (MRB)............................................................................. 172

7.2.3

DTC Source Address Register (SAR).................................................................. 173

HD64F2149YV 数据表(PDF) 14 Page - Renesas Technology Corp

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