HD64F2149YV datasheet(24/1075 Pages) RENESAS

24 / 1075 page

Rev. 3.00 Jan 18, 2006 page xxiv of xxviii

18B.3.3 A20 Gate .......................................................................................................... 638

18B.3.4 Host Interface Shutdown Function (LPCPD)................................................... 641

18B.3.5 Host Interface Serialized Interrupt Operation (SERIRQ) ................................ 645

18B.3.6 Host Interface Clock Start Request (CLKRUN) .............................................. 647

18B.4 Interrupt Sources.............................................................................................................. 648

18B.4.1 IBF1, IBF2, IBF3, ERRI .................................................................................. 648

18B.4.2 SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12....................................................... 648

18B.5 Usage Note....................................................................................................................... 650

Section 19 D/A Converter................................................................................................. 653

19.1

Overview........................................................................................................................... 653

19.1.1 Features................................................................................................................ 653

19.1.2 Block Diagram ..................................................................................................... 654

19.1.3 Input and Output Pins .......................................................................................... 655

19.1.4 Register Configuration......................................................................................... 655

19.2

Register Descriptions ........................................................................................................ 656

19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 656

19.2.2 D/A Control Register (DACR) ............................................................................ 656

19.2.3 Module Stop Control Register (MSTPCR) .......................................................... 658

19.3

Operation .......................................................................................................................... 659

Section 20 A/D Converter................................................................................................. 661

20.1

Overview........................................................................................................................... 661

20.1.1 Features................................................................................................................ 661

20.1.2 Block Diagram ..................................................................................................... 662

20.1.3 Pin Configuration................................................................................................. 663

20.1.4 Register Configuration......................................................................................... 664

20.2

Register Descriptions ........................................................................................................ 664

20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 664

20.2.2 A/D Control/Status Register (ADCSR) ............................................................... 665

20.2.3 A/D Control Register (ADCR) ............................................................................ 668

20.2.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 669

20.2.5 Module Stop Control Register (MSTPCR) .......................................................... 670

20.3

Interface to Bus Master ..................................................................................................... 671

20.4

Operation .......................................................................................................................... 672

20.4.1 Single Mode (SCAN = 0) .................................................................................... 672

20.4.2 Scan Mode (SCAN = 1)....................................................................................... 674

20.4.3 Input Sampling and A/D Conversion Time ......................................................... 676

20.4.4 External Trigger Input Timing ............................................................................. 677

20.5

Interrupts ........................................................................................................................... 677

20.6

Usage Notes ...................................................................................................................... 678

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