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HD64F2149YV 数据表(PDF) 79 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 79 Page - Renesas Technology Corp |
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79 / 1075 page  Section 2 CPU Rev. 3.00 Jan 18, 2006 page 51 of 1044 REJ09B0280-0300 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Function Instruction MOV BWL BWL BWL BWL BWL BWL B BWL — BWL ———— POP, PUSH ————————————— WL LDM* 3, STM*3 ————————————— L Data transfer MOVFPE* 1, MOVTPE*1 ——————— B —————— ADD, CMP BWL BWL ———————————— SUB WL BWL ———————————— ADDX, SUBX B B ———————————— ADDS, SUBS — L ———————————— INC, DEC — BWL ———————————— DAA, DAS — B ———————————— MULXU, DIVXU — BW ———————————— MULXS, DIVXS — BW ———————————— NEG — BWL ———————————— EXTU, EXTS — WL ———————————— Arithmetic operations TAS* 2 —— B ——————————— AND, OR, XOR BWL BWL ———————————— Logic operations NOT — BWL ———————————— Shift — BWL ———————————— Bit manipulation — BB ——— BB — B ———— Bcc, BSR —————————— —— JMP, JSR ———————— ——— — Branch RTS ————————————— TRAPA ————————————— RTE ————————————— SLEEP ————————————— LDC B B WWWW — W — W ———— STC — B WWWW — W — W ———— ANDC, ORC, XORC B ————————————— System control NOP ————————————— Block data transfer — ———————————— BW Legend: B: Byte, W: Word, L: Longword Notes: 1. Cannot be used in the H8S/2169 or H8S/2149. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. |
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