HD64F2149YV datasheet(78/1075 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 50 of 1044

REJ09B0280-0300

2.6

Instruction Set

2.6.1

Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in

table 2.1.

Table 2.1

Instruction Classification

Function

Instructions

Size

Types

Data transfer

MOV

BWL

POP*

1, PUSH*1

LDM*

5, STM*5

MOVFPE*

3, MOVTPE*3

Arithmetic

ADD, SUB, CMP, EG

BWL

operations

ADDX, SUBX, DAA, DAS

INC, DEC

BWL

ADDS, SUBS

MULXU, DIVXU, MULXS, DIVXS

EXTU, EXTS

TAS*

Logic operations

AND, OR, XOR, NOT

BWL

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR

BWL

Bit manipulation

BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR

B14

Branch

Bcc*

2, JMP, BSR, JSR, RTS

—

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —

Block data transfer EEPMOV

—

Total: 65 types

Legend:

B: Byte

W: Word

L: Longword

Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP.

POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,

@-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in the H8S/2169 or H8S/2149.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

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