HD64F2149YV datasheet(13/1075 Pages) RENESAS

13 / 1075 page

Rev. 3.00 Jan 18, 2006 page xiii of xxviii

Section 5 Interrupt Controller .......................................................................................... 101

5.1

Overview........................................................................................................................... 101

5.1.1

Features................................................................................................................ 101

5.1.2

Block Diagram ..................................................................................................... 102

5.1.3

Pin Configuration................................................................................................. 103

5.1.4

5.2

Register Descriptions ........................................................................................................ 105

5.2.1

System Control Register (SYSCR) ...................................................................... 105

5.2.2

Interrupt Control Registers A to C (ICRA to ICRC)............................................ 106

5.2.3

IRQ Enable Register (IER) .................................................................................. 107

5.2.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 107

5.2.5

IRQ Status Register (ISR).................................................................................... 108

5.2.6

Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 110

5.2.7

Keyboard Matrix Interrupt Mask Register A (KMIMRA) Wakeup Event

Interrupt Mask Registr B (WUEMRB) ................................................................ 110

5.2.8

Address Break Control Register (ABRKCR)....................................................... 113

5.2.9

Break Address Registers A to C (BARA to BARC) ............................................ 114

5.3

Interrupt Sources ............................................................................................................... 115

5.3.1

External Interrupts ............................................................................................... 115

5.3.2

Internal Interrupts................................................................................................. 117

5.3.3

Interrupt Exception Vector Table ........................................................................ 118

5.4

Address Breaks ................................................................................................................. 121

5.4.1

Features................................................................................................................ 121

5.4.2

Block Diagram ..................................................................................................... 121

5.4.3

Operation ............................................................................................................. 122

5.4.4

Usage Notes ......................................................................................................... 122

5.5

Interrupt Operation............................................................................................................ 124

5.5.1

Interrupt Control Modes and Interrupt Operation ................................................ 124

5.5.2

Interrupt Control Mode 0 ..................................................................................... 127

5.5.3

Interrupt Control Mode 1 ..................................................................................... 129

5.5.4

Interrupt Exception Handling Sequence .............................................................. 132

5.5.5

Interrupt Response Times .................................................................................... 133

5.6

Usage Notes ...................................................................................................................... 134

5.6.1

Contention between Interrupt Generation and Disabling..................................... 134

5.6.2

Instructions that Disable Interrupts ...................................................................... 135

5.6.3

Interrupts during Execution of EEPMOV Instruction.......................................... 135

5.7

DTC Activation by Interrupt............................................................................................. 136

5.7.1

Overview.............................................................................................................. 136

5.7.2

Block Diagram ..................................................................................................... 136

5.7.3

Operation ............................................................................................................. 137

HD64F2149YV 数据表(PDF) 13 Page - Renesas Technology Corp

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