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HD64F2149YV 数据表(PDF) 97 Page - Renesas Technology Corp

部件名 HD64F2149YV
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 97 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 3.00 Jan 18, 2006 page 69 of 1044
REJ09B0280-0300
End of bus request
Bus request
Program execution
state
Bus-released state
Sleep mode
Exception-handling state
External interrupt
Software standby mode
RES = high
Reset state
STBY = high, RES = low
Hardware standby mode*2
Power-down state*3
*1
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when
STBY goes low.
The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 24, Power-Down State.
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Interrupt
request
End of bus
request
Bus
request
Request for
exception
handling
End of
exception
handling
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Figure 2.15 State Transitions
2.8.2
Reset State
When the
RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are disabled in the reset state. Reset exception handling starts when the
RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14,
Watchdog Timer (WDT).



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