HD64F2149YV datasheet(62/1075 Pages) RENESAS

62 / 1075 page

Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 34 of 1044

REJ09B0280-0300

• High-speed operation

 All frequently-used instructions execute in one or two states

 Maximum clock rate:

10 MHz

 8/16/32-bit register-register add/subtract: 100 ns

 8 × 8-bit register-register multiply:

1200 ns

 16 ÷ 8-bit register-register divide:

1200 ns

 16 × 16-bit register-register multiply:

2000 ns

 32 ÷ 16-bit register-register divide:

2000 ns

• Two CPU operating modes

 Normal mode

 Advanced mode

• Power-down state

 Transition to power-down state by SLEEP instruction

 CPU clock speed selection

2.1.2

Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states

The number of execution states of the MULXU and MULXS instructions differ as follows.

Number of Execution States

Instruction

Mnemonic

H8S/2600

H8S/2000

MULXU

MULXU.B Rs, Rd

MULXU.W Rs, ERd

MULXS

MULXS.B Rs, Rd

MULXS.W Rs, ERd

There are also differences in the address space, EXR register functions, power-down state, etc.,

depending on the product.

HD64F2149YV 数据表(PDF) 62 Page - Renesas Technology Corp

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