HD64F2149YV datasheet(86/1075 Pages) RENESAS

86 / 1075 page

Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 58 of 1044

REJ09B0280-0300

Type

Instruction

Size*

Function

Branch

instructions

Bcc

—

Branches to a specified address if a specified condition

is true. The branching conditions are listed below.

Mnemonic

Description

Condition

BRA(BT)

Always (true)

Always

BRN(BF)

Never (false)

Never

BHI

High

∨ Z = 0

BLS

Low or same

∨ Z = 1

BCC(BHS)

Carry clear

(high or same)

C = 0

BCS(BLO)

Carry set (low)

C = 1

BNE

Not equal

Z = 0

BEQ

Equal

Z = 1

BVC

Overflow clear

V = 0

BVS

Overflow set

V = 1

BPL

Plus

N = 0

BMI

Minus

N = 1

BGE

Greater or equal

⊕ V = 0

BLT

Less than

⊕ V = 1

BGT

Greater than

∨(N ⊕ V) = 0

BLE

Less or equal

∨(N ⊕ V) = 1

JMP

—

Branches unconditionally to a specified address.

BSR

—

Branches to a subroutine at a specified address.

JSR

—

Branches to a subroutine at a specified address.

RTS

—

Returns from a subroutine

TRAPA

—

Starts trap-instruction exception handling.

RTE

—

Returns from an exception-handling routine.

System

control

instructions

SLEEP

—

Causes a transition to a power-down state.

LDC

B/W

(EAs)

→ CCR, (EAs) → EXR

Moves contents of a general register or memory or

immediate data to CCR or EXR. Although CCR and EXR

are 8-bit registers, word-size transfers are performed

between them and memory. The upper 8 bits are valid.

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