HD64F2149YV datasheet(20/1075 Pages) RENESAS

20 / 1075 page

Rev. 3.00 Jan 18, 2006 page xx of xxviii

13.2.5 Module Stop Control Register (MSTPCR) .......................................................... 394

13.3

Operation .......................................................................................................................... 395

13.3.1 PWM Decoding (PDC Signal Generation) .......................................................... 395

13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 397

13.3.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 398

13.3.4 IHI Signal and 2fH Modification ......................................................................... 400

13.3.5 IVI Signal Fall Modification and IHI Synchronization ....................................... 402

13.3.6 Internal Synchronization Signal Generation

(IHG/IVG/CL4 Signal Generation) ..................................................................... 403

13.3.7 HSYNCO Output ................................................................................................. 406

13.3.8 VSYNCO Output ................................................................................................. 407

13.3.9 CBLANK Output ................................................................................................. 408

Section 14 Watchdog Timer (WDT).............................................................................. 409

14.1

Overview........................................................................................................................... 409

14.1.1 Features................................................................................................................ 409

14.1.2 Block Diagram ..................................................................................................... 410

14.1.3 Pin Configuration................................................................................................. 411

14.1.4 Register Configuration......................................................................................... 412

14.2

Register Descriptions ........................................................................................................ 412

14.2.1 Timer Counter (TCNT)........................................................................................ 412

14.2.2 Timer Control/Status Register (TCSR) ................................................................ 413

14.2.3 System Control Register (SYSCR) ...................................................................... 416

14.2.4 Notes on Register Access..................................................................................... 417

14.3

Operation .......................................................................................................................... 418

14.3.1 Watchdog Timer Operation ................................................................................. 418

14.3.2 Interval Timer Operation ..................................................................................... 419

14.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 420

14.3.4

RESO Signal Output Timing ............................................................................... 421

14.4

Interrupts ........................................................................................................................... 421

14.5

Usage Notes ...................................................................................................................... 422

14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 422

14.5.2 Changing Value of CKS2 to CKS0...................................................................... 423

14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 423

14.5.4 System Reset by

RESO Signal............................................................................. 423

14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode,

and Watch Mode .................................................................................................. 424

14.5.6 OVF Flag Clear Condition ................................................................................... 424

Section 15 Serial Communication Interface (SCI, IrDA) ........................................ 425

15.1

Overview........................................................................................................................... 425

HD64F2149YV 数据表(PDF) 20 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 20 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载