HD64F2149YV datasheet(91/1075 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 63 of 1044

REJ09B0280-0300

Table 2.5 indicates the accessible absolute address ranges.

Table 2.5

Absolute Address Access Ranges

Absolute Address

Normal Mode

Advanced Mode

Data address

8 bits (@aa:8)

H'FF00 to H'FFFF

H'FFFF00 to H'FFFFFF

16 bits (@aa:16)

H'0000 to H'FFFF

H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32)

H'000000 to H'FFFFFF

Program instruction

address

24 bits (@aa:24)

Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or

32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and

added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch

address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the

displacement is added is the address of the first byte of the next instruction, so the possible

branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to

+16384 words) from the branch instruction. The resulting value should be an even number.

Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The upper bits of the absolute address are all assumed to be 0,

so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in

advanced mode). In normal mode the memory operand is a word operand and the branch address

is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of

which is assumed to be all 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further details,

refer to section 4, Exception Handling.

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