HD64F2149YV datasheet(99/1075 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 71 of 1044

REJ09B0280-0300

Figure 2.16 shows the stack after exception handling ends.

Note: * Ignored when returning.

CCR

(24 bits)

CCR

CCR*

(16 bits)

Normal mode

Advanced mode

Figure 2.16 Stack Structure after Exception Handling (Examples)

2.8.4

Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5

Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. While the bus is released, all CPU internal operations are halted.

There is one other bus master in addition to the CPU: the data transfer controller (DTC).

For further details, refer to section 6, Bus Controller.

2.8.6

Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,

software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also

three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In

medium-speed mode, the CPU and other bus masters operate on a medium-speed clock. Module

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